Question: Given the following Verilog: logic x[7:0] ; assign x = 8'b0101_1010 ; what is the value of x[4]?

Answer: 1

Question: Given the following Verilog: logic x[7:0] ; assign x = 8'b0101_1010 ; what is the value of x[5]?

Answer: 0

Question: Given the following Verilog: logic x[7:0] ; assign x = 8'b0101_1010 ; what is the value of x[6]?

Answer: 1

Question: Write the Verilog module statement for a module named mod1 that has one 3-bit logic input named x and a 4-bit logic output named y. Include everything from the module keyword to the semicolon (;).

Answer: module mod1 ( input logic [2:0] x, output logic [3:0] y ) ;

Question: Write the Verilog module statement for a module named mod1 that has one 4-bit logic input named x and a 3-bit logic output named y. Include everything from the module keyword to the semicolon (;).

Answer: module mod1 ( input logic [3:0] x, output logic [2:0] y ) ;

Question: Write an assign statement that would implement the circuit shown above. Your answer should begin with assign y=, include the signals in the order a, b, c, d and end with a semicolon (;). Use only the following operators and parentheses: ~ is NOT & is AND | is OR ^ is XOR

Answer: assign y = a & b | c ^ d ; OR assign y = ( a & b | c ) & d ; (bug in marking code), parentheses optional

Question: always_comb begin unique case (c) 2'b00: o = p ; 2'b01: o = 4'h5 ; 2'b10: o = 4'h7 ; 2'b11: o = b ; endcase end What would you need to substitute for A, B and C in the schematic above so that it matches the Verilog above? Give the corresponding signal names in that order: first the signal name corresponding to A then the one corresponding to B then the one corresponding to C. Note: the multiplexer inputs are labelled with the value of theselect input required to select that input.

Answer: c o p

Question: always_comb begin unique case (m) 2'b00: x = c ; 2'b01: x = 4'h5 ; 2'b10: x = 4'h7 ; 2'b11: x = b ; endcase end What would you need to substitute for A, B and C in the schematic above so that it matches the Verilog above? Give the corresponding signal names in that order: first the signal name corresponding to A then the one corresponding to B then the one corresponding to C. Note: the multiplexer inputs are labelled with the value of theselect input required to select that input.

Answer: m x c

Question: always_comb begin unique case (s) 2'b00: y = a ; 2'b01: y = 4'h5 ; 2'b10: y = 4'h7 ; 2'b11: y = b ; endcase end What would you need to substitute for A, B and C in the schematic above so that it matches the Verilog above? Give the corresponding signal names in that order: first the signal name corresponding to A then the one corresponding to B then the one corresponding to C. Note: the multiplexer inputs are labelled with the value of theselect input required to select that input.

Answer: s y a

Question: always_comb begin if ( A ) o = 8'h0 ; else if ( B ) o = a+1 ; else o = a ; end What would you need to substitute for A and B in the Verilog code above so that the Verilog above matches the schematic above? Your answer should be the values of A and B, in that order, separated with a space.

Answer: either x y or y x were marked correct (bug in marking code)

Question: always_comb begin unique case (x) 2'b00: y = 4'ha ; 2'b01: y = 4'hb ; 2'b10: y = 4'hc ; 2'b11: y = 4'hd ; endcase end Given the Verilog code above, if the signal x has the value 0 (decimal) what is the value of y? Give your answer as a decimal number (not in Verilog syntax).

Answer: 10

Question: always_comb begin unique case (x) 2'b00: y = 4'ha ; 2'b01: y = 4'hb ; 2'b10: y = 4'hc ; 2'b11: y = 4'hd ; endcase end Given the Verilog code above, if the signal x has the value 1 (decimal) what is the value of y? Give your answer as a decimal number (not in Verilog syntax).

Answer: 11

Question: always_comb begin unique case (x) 2'b00: y = 4'ha ; 2'b01: y = 4'hb ; 2'b10: y = 4'hc ; 2'b11: y = 4'hd ; endcase end Given the Verilog code above, if the signal x has the value 2 (decimal) what is the value of y? Give your answer as a decimal number (not in Verilog syntax).

Answer: 12

Question: always_comb begin unique case (x) 2'b00: y = 4'ha ; 2'b01: y = 4'hb ; 2'b10: y = 4'hc ; 2'b11: y = 4'hd ; endcase end Given the Verilog code above, if the signal x has the value 3 (decimal) what is the value of y? Give your answer as a decimal number (not in Verilog syntax).

Answer: 13

Question: What is the Verilog numeric literal for an 5-bit number with a decimal value of 5 using base 10 (decimal)?

Answer: 5'd5

Question: What is the Verilog numeric literal for an 5-bit number with a decimal value of 8 using base 2 (binary)?

Answer: 5'b01000

Question: What is the Verilog numeric literal for an 6-bit number with a decimal value of 4 using base 2 (binary)?

Answer: 'b000100

Question: What is the Verilog numeric literal for an 7-bit number with a decimal value of 6 using base 16 (hexadecimal)?

Answer: 7'h6